The PPC DOOR System Development Suite accelerates system integration, validation, and bring-up with a set of four connected platforms for concurrent HW/SW design and verification. Its technologies span the entire design cycle, from early architectural-level software development through testbench simulation and system validation to prototyping. It is open for third-party integration and supports industry standards and multiple levels of design abstraction. It allows easy migration among the four platforms and between HW/SW domains. And, it can scale to meet performance, capacity, and volume needs as they expand.

Each of the four platforms is optimized for a different part of the system development flow.

The Virtual System Platform is a new solution for early software development at the architectural and prototype design phases. It provides an integrated HW/SW debug environment with unique multi-core capabilities, it is connected to the RTL verification flow, and it automates and accelerates the creation of new transaction-level models (TLMs). While ideal for pre-RTL, architectural-level software development, the Virtual System Platform can also be used in a post-RTL mode to generate virtual prototypes that provide an alternative to reference boards.

・Based on SystemC TLM 2.0 and IEEE 1666 standard

・Supports third-party processor models (ARM Fast Models, Imperas OVP models)

・Supports third-party software debuggers (ARM, Lauterbach, GDB)

・Scales from single-core to multi-core software development and debug with performance reaching hundreds of MHz

Well-known for many years, the Incisive Verification Platform is a complete family of tools optimized for block- and chip-level verification with testbench simulation as a focal point. It also includes technologies for verification planning and management, verification IP creation and reuse, mixed-signal simulation, and formal analysis. Incisive Software Extensions generate a system testbench with access to the software executing on processor models, thus allowing software driver verification. The Incisive Verification Platform also provides a metric-driven verification flow, which starts with an executable verification plan, collects and analyzes coverage metrics, and makes changes as needed to reach closure.

・Supports e, SystemC, and SystemVerilog languages

・Supports the acceleration-ready Universal Verification Methodology (UVM)

・Provides the SimVision debug user interface used by all other Platforms in the Suite

・Supports a mixed-signal environment

The Verification Computing Platform (Palladium XP) performs advanced simulation acceleration and emulation in a single environment, with hot-swap capability for instant migration among tasks. Ideal for long regression tests and system validation, it performs HW/SW co-verification and offers flexible support for hard/soft IP. The Verification Computing Platform’s transaction-based acceleration capabilities, combined with Accelerated Verification IP, speed up a metric-driven UVM-based verification flow through multiple interfaces and third-party tools.

・Supports e, SystemC, and SystemVerilog languages, the UVM, and Accellera SCE-MI

・Offers configurations up to 2 billion gates and up to 4 MHz speed

・Supports dynamic power analysis and low-power verification

・Supports up to 512 simultaneous users with a granularity of 4M gates

This new FPGA-based prototyping solution combines high-capacity FPGA boards with a complete implementation and debug software flow. Ideal for exhaustive regression tests and cycle-accurate software development, the Rapid Prototyping Platform speeds bring-up time, automates multi-FPGA partitioning, and includes a powerful debug capability.

・Uses an ASIC RTL-based flow with standard design languages

・Supports standard interfaces (PCI Express, Ethernet, USB)

・Altera Stratix IV hardware and software is embedded

・Scales up to 30M ASIC gates and tens of MHz execution speed